1. Field of the Invention
This invention relates to semiconductor device manufacturing, and more particularly, to an improved method and system for polishing a semiconductor topography.
2. Description of the Related Art
The following descriptions and examples are not admitted to be prior art by virtue of their inclusion within this section.
Fabrication of an integrated circuit involves numerous processing steps. For example, isolation regions may be formed in a semiconductor substrate to separate subsequently formed active regions of the substrate. In addition, after implant regions (e.g., source/drain regions) have been placed within a semiconductor substrate and gate areas defined upon the substrate, an interlevel dielectric may be formed across the topography to isolate the gate areas and the implant regions from overlying conductors. Interconnect routing may be placed over the interlevel dielectric and connected to the implant regions and/or the gate areas by ohmic contacts formed through the interlevel dielectric. Alternating levels of interlevel dielectric and interconnect may be placed across the semiconductor topography to form a multi-level integrated circuit.
Forming substantially planar upper surfaces of a semiconductor topography during intermediate process steps may facilitate fabrication of layers and structures that meet design specifications. For example, a dielectric layer may be formed across a previously patterned layer of a semiconductor topography using a process such as chemical vapor deposition (“CVD”). Such a dielectric layer may be used to form an interlevel dielectric or shallow trench isolation regions. Elevational disparities of the deposited dielectric layer may be reduced by polishing the deposited dielectric layer using a process such as chemical mechanical polishing (“CMP”). In addition, a contact opening may be formed within a polished dielectric layer and subsequently filled with a layer of conductive material. In this manner, the layer of conductive material may be formed within the contact opening and on an upper surface of the polished dielectric layer. As such, the layer of conductive material may also be polished such that an upper surface of the contact structure may be relatively level with an upper surface of the dielectric layer.
Additional layers and structures may be formed upon such layers and structures. The additional layers and structures may include, for example, additional dielectric layers, additional contact structures, local interconnect wires, and/or metallization layers. In this manner, the polished upper surface of the dielectric layer and/or structures may facilitate the formation of such additional layers and structures having uniform vertical and lateral dimensions. For example, polishing the semiconductor topography may facilitate the formation of local interconnect structures having a substantially uniform thickness by providing a relatively planar surface upon which a dielectric material may be deposited to insulate adjacent local interconnect structures.
Moreover, polishing the semiconductor topography may aid in forming local interconnect structures having uniform lateral dimensions by providing a level surface upon which a patterned masking layer may be formed. For example, substantially planar surfaces may become increasingly important as the feature sizes of semiconductor devices are reduced, since the depth of focus required to pattern an upper surface of a semiconductor topography may increase with reductions in feature size. In addition, if a topography is non-planar, the patterned image may be distorted and the intended structure may not be formed to the specifications of the device. In particular, correctly patterning layers upon a topological surface containing elevational “hill” or “valley” areas may be difficult using optical lithography since the all parts of the topography must be within the depth of focus of the lithography system. In this manner, a masking layer may be accurately patterned by a lithography technique such that the pattern may be accurately transferred to a dielectric layer to form local interconnect structures.
Forming a substantially planar upper surface of such layers and structures may play an important role in the functionality of a semiconductor device. For example, problems with step coverage may arise when a dielectric, conductive, or semiconductive material is deposited over a topological surface having elevationally raised regions. Step coverage is defined as a measure of how well a film conforms over an underlying step and is expressed by the ratio of the minimum thickness of a film as it crosses a step to the nominal thickness of the film over horizontal regions. In another embodiment, polishing a semiconductor topography may include forming shallow trench isolation regions with substantially planar surfaces such that the aforementioned additional layers and structures may be formed with uniform thickness and with lateral dimensions within specification. Accordingly, layers and structures of a semiconductor device may be formed having dimensions, which are approximately equal to the design specifications of the semiconductor device.
As mentioned above, CMP is a technique commonly employed to polish or remove the elevational fluctuations in the surface of a semiconductor topography. A conventional CMP process may involve placing a semiconductor wafer against a backing plate of a wafer carrier in order to hold the wafer relative to an underlying polishing pad. The wafer may then be pressed face-down toward the polishing pad which lies on or is attached to a support structure. During the CMP process, the polishing pad and/or the wafer carrier may be set in motion as the wafer is forced against the pad. For example, the polishing pad and the wafer carrier may be placed on a rotatable table such that the wafer and the polishing pad may be rotated relative to each other. Alternatively, the wafer carrier may be rotated relative to a fixed pad or vice versa. In another embodiment, the polishing pad may be a belt, which traverses against a fixed or rotating wafer. In either embodiment, the rotatable table, fixed pad, or belt may serve as the support structure to which the polishing pad lies upon or is attached.
An abrasive, fluid-based chemical suspension, often referred to as a “slurry,” may be deposited onto the surface of the polishing pad. The slurry fills the space between the polishing pad and the wafer surface such that a chemical in the slurry may react with the surface material being polished. The movement of the polishing pad relative to the wafer causes abrasive particles entrained within the slurry to physically strip the reacted surface material from the wafer. In addition, the pad itself may physically remove some material from the surface of the semiconductor topography. Therefore, the process may employ a combination of chemical stripping and mechanical polishing to form a relatively level surface.
During polishing with a slurry, defects such as microscratches may be formed on the surface of a topography. Microscratches may include scratches of any length having a width of less than about 0.5 μm. Such microscratches may have a depth of up to about 100 Å and may be relatively difficult to remove during final stages of polishing on a final pad. Such final pad polishing my be designed to remove relatively little material from a topography thereby essentially “smoothing” an upper surface of the topography. Therefore, such microscratches may remain on the topography and may increase reliability failures of a device formed on the topography. For example, if conductive material resides in a microscratch that extends across a width of a dielectric material between two conductive structures, a short may be formed between the two conductive structures. Other such reliability failures may also be caused by such microscratches.
Accordingly, it would be advantageous to develop a method and a system for reducing the number of microscratches formed on a semiconductor topography during polishing.